1. Field of the Invention
The present invention relates to an adaptive bias circuit, and more particularly, to an adaptive bias circuit for adaptively biasing a system.
2. Description of the Prior Art
At present, electronic devices are ubiquitous. They can be found in nearly every place imaginable, including the home, the workplace, vehicles, and even our pockets. And, as electronic device technologies mature, for the same cost, the electronic devices become more portable, use less power, and offer greater functionality. In part, this is due to availability of smaller geometry electronic components, such as transistors and on-chip capacitors. However, novel circuit architectures with improved specifications are also responsible for overall performance gains in the electronic devices.
Amplifiers are a key component in practically every electronic device. They vary broadly in their electrical characteristics, such as gain, bandwidth, and linearity, and vary even more in their application to active filters, buffers, analog-to-digital converters, and RF transceivers.
Currently, most amplifiers used in integrated circuits use a transistor, or transistors, for providing signal amplification. In some applications, such as power amplifiers for RF transceivers, linear operation of the amplifying transistor(s) is an important design consideration. To achieve linear operation of the amplifying transistor(s), a bias circuit is coupled to the amplifier to provide a bias current or voltage to the amplifying transistor(s). Typically, the bias current or voltage is selected to maximize a linear operating region while minimizing the current consumption of the amplifying transistor(s).
One technique used to increase the linear operating region of the amplifying transistor(s) is adaptive biasing. Instead of biasing the amplifying transistor(s) with a fixed bias current or voltage, an adaptive bias circuit is utilized to provide more or less DC current or voltage based on characteristics of the input signal, such as amplitude, phase, frequency, etc. The adaptive bias circuit may also be used in conjunction with a traditional bias circuit, in effect providing fine-tuning of the bias current or voltage provided.
Please refer to FIG. 1, which is a diagram of an adaptive bias circuit according to the prior art. In the prior art, the adaptive bias circuit biases a power amplifier transistor Q1 that outputs an output signal through an output matching circuit. The adaptive bias circuit has a bias transistor Q2, a first bias resistor R1, a first bias diode D1, and a second bias diode D2. A collector of the bias transistor Q2 is coupled to a power supply voltage Vcc. An emitter of the bias transistor Q2 is coupled to a base of the power amplifier transistor Q1. A first bias resistor R1 is coupled between a bias reference voltage Vbias and a base of the bias transistor Q2. An anode of the first bias diode D1 is coupled to the base of the bias transistor Q2 and a cathode of the first bias diode D1 is coupled to an anode of the second bias diode D2. A cathode of the second bias diode D2 is coupled to ground.
As power of an input signal received through a capacitor C1 increases, i.e. power at the emitter of the bias transistor Q2 increases, the bias transistor Q2 emits more adaptive bias current to the base of the power amplifier transistor Q1 to maintain operation in a linear region. The required adaptive bias current to keep a power amplifier transistor operating linearly depends on the characteristics of the power amplifier transistor itself and the matching circuit coupled to the power amplifier.
In some cases, as the input power increases, the adaptive bias current provided by the emitter of the bias transistor Q2 may not be large enough to keep the amplifier operating in the linear region. In such a case, an improved adaptive bias circuit is needed to provide an adaptive bias current that is more sensitive to the input power level.
Please refer to FIG. 4, which is a diagram of a bias circuit according to the prior art. The bias circuit shown in FIG. 4 is disclosed in U.S. Pat. No. 6,859,103 (hereafter '103), entitled “Bias Circuit for Improving Linearity of a Radio Frequency Power Amplifier,” and comprises a bias transistor 412 biased by two diodes 401, 402 and a resistor 403. The bias transistor 412 provides bias current to a power amplifier transistor 422. RF input is applied to a base of the power amplifier transistor 422, and is partially isolated from an emitter of the bias transistor 412 by an inductor 404. An LC series-connected resonator circuit 405, 406 conducts a second harmonic of the RF input to ground. This architecture emits more adaptive bias current with increased input power through the bias transistor 412, but is not able to provide an agile adaptive current response with changes in the input power.
Please refer to FIG. 5, which is a diagram of a bias circuit according to the prior art. The bias circuit shown in FIG. 5 is disclosed in U.S. Pat. No. 6,744,321, entitled “Bias Control Circuit for Power Amplifier,” and comprises a primary bias circuit 502 for biasing a power amplifier transistor 501. The bias circuit further comprises a supplementary bias circuit 504, which is turned on or off through a control voltage Vcom, and provides supplemental bias current to the power amplifier transistor 501. The bias circuit shown in FIG. 5 only allows for two possible power modes: a lower output power mode, and a high output power mode, and more transistors must be added if more power modes are required. Further, the power mode is decided by the control voltage Vcom, which implies that extra circuitry is required to provide the voltage Vcom, and to determine when to switch the voltage Vcom.